Application Specific Integrated Circuits for Bioengineering

Module aims

In this module you will be introduced to the basics of simulation, physical layout and verification of Application Specific Integrated Circuits (ASICs) for Bioengineering applications. You will have the opportunity to practice the application of good layout techniques for passive and active components of an ASIC and to practice the application of modular and hierarchical layout of an ASIC.

Learning outcomes

Upon successful completion of this module you will be able to: Discuss the importance of the ‘design rules’ of a technology when laying-out. Discuss the significance and impact of good and bad layouts on high-fidelity design-to-spec. Employ good layout techniques for active and passive components. Explain the ASIC tape-out process. Create modular designs and layouts of small IC blocks (e,g. current mirrors, differential pairs). Create hierarchical design and layout of larger IC blocks (e.g. OTAs, Op-Amps). Assess the role of typical industry applied simulations e.g. Monte Carlo, Post-layout. Produce a CADENCE simulation, layout and verification of ASICs and iterative layouts to achieve ‘Design Rule Check clear’.

Module syllabus

Technology and IC Layout (Lectures): IC fabrication errors (random and systematic); Matching techniques for passive and active components; Monte Carlo (MC) evaluation, process corners etc; ESD protection, pads and pads’ ring; Overview of IC tape-out flowchart. High-fidelity simulation of ICs (CAD LAB): Familiarisation with simulation tools. Single NMOS/PMOS characteristics. Common-source amplifier; timeand frequency-domain simulations. Differential pair; DC-characteristics; differential and common-mode simulations. Layout of ASICs (CAD LAB): Familiarisation with layout tools (layout editor) and DRC (Design Rules Check) procedure. Layout of passive components; MC evaluation for good and bad matching of passive components. Layout of active devices; MC evaluation for good and bad matching of active components. LVS (Layout vs. Schematic) procedure of small modules. Post-layout simulation. Pads.

Teaching methods

Students will be taught over one terms using a combination of lectures and practical CAD lab sessions. Lecture sessions will be made available on Panopto for review and supplemented with technologies to promote active engagement during the lecture such as 'learning catalytics'. Lab activities and study groups will be based on taught content from lectures to reinforce these topics and allow students to test their understanding. Lab and study groups will also allow students opportunities for paired and small group learning and to share their experience and understanding with other students.

Assessments

The LOs for this module will be assessed in part by a progress test with the LOs covering practical aspects of the modules assessed by three courseworks.